Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

US7115965B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Herbert L. Ho · New Windsor, US
• Mahender Kumar · Hopewell Junction, US
• Qiqing C. Ouyang · Yorktown Heights, US
• Paul A. Papworth · Wappingers Falls, US
• Christopher D. Sheraw · Wappingers Falls, US
• Michael D. Steigerwalt · Newburgh, US

Key dates

• Filing date: Sep 1, 2004
• Grant date: Oct 3, 2006
• Expiry date: Sep 1, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.