Integrated circuit with self-aligned line and via and manufacturing method therefor
US7119010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2002 |
| Grant date | Oct 10, 2006 |
| Priority date | — |
| Expiry date | Sep 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.