Alex See
14Patents
8h-index
27Co-inventors
64Inventor score
Filing activity: Oct 2, 2000 → Aug 21, 2006
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6406975B1 | Method for fabricating an air gap shallow trench isolation (STI) structure | Electricity | 51 | Expired |
| US7094669B2 | Structure and method of liner air gap formation | Electricity | 34 | Expired |
| US6380106B1 | Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures | Electricity | 34 | Expired |
| US6558994B2 | Dual silicon-on-insulator device wafer die | Emerging Cross-Sectional Technologies | 31 | Expired |
| US6380084B1 | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling | Electricity | 27 | Expired |
| US6410429B1 | Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions | Electricity | 14 | Expired |
| US7585768B2 | Combined copper plating method to improve gap fill | Electricity | 11 | Active |
| US6613649B2 | Method for buffer STI scheme with a hard mask layer as an oxidation barrier | Electricity | 8 | Expired |
| US7119010B2 | Integrated circuit with self-aligned line and via and manufacturing method therefor | Electricity | 6 | Expired |
| US7989338B2 | Grain boundary blocking for stress migration and electromigration improvement in CU interconnects | Electricity | 6 | Active |
| US6849928B2 | Dual silicon-on-insulator device wafer die | Emerging Cross-Sectional Technologies | 5 | Expired |
| US6518133B1 | Method for fabricating a small dimensional gate with elevated source/drain structures | Electricity | 4 | Expired |
| US8766454B2 | Integrated circuit with self-aligned line and via | Electricity | 1 | Active |
| US9318378B2 | Slot designs in wide metal lines | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.