Implantation method to improve ESD robustness of thick gate-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies

US7119405B2 · kind B2 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Jau-Wen Chen · Cupertino, US
• Yoon Huh · Seoul, KR
• Erhong Li · Sunnyvale, US

Key dates

• Filing date: Feb 11, 2005
• Grant date: Oct 10, 2006
• Expiry date: Feb 11, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/813

Abstract

An implantation method to improve ESD robustness of thick-oxide grounded-gate NMOSFET's in deep-submicron CMOS technologies. Based on standard process flow in DGO, a thick gate-oxide ESD device is improved. Instead of using the standard I/O device, the ESD device uses the thin-oxide N-LDD implantation, and thus its ESD robustness is enhanced. This is performed by updating the logic Boolean operations of thick gate-oxide and thin gate-oxide N-LDD before fabricating the masks. In TGO, the intermediate-oxide ESD uses thin-oxide N-LDD implantation, and the thick-oxide ESD uses intermediate-oxide N-LDD implantation.