Method for achieving increased control over interconnect line thickness across a wafer and between wafers
US7122465B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Oct 17, 2006 |
| Priority date | — |
| Expiry date | Dec 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.