Inclusion of low-k dielectric material between bit lines
US7125790B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2003 |
| Grant date | Oct 24, 2006 |
| Priority date | — |
| Expiry date | Oct 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
Abstract
Low-k dielectric materials are incorporated as an insulator material between bit lines and an inter-level dielectric material. The device is first processed in a known manner, up to and including the deposition and anneal of the bit line metal, using a higher dielectric constant material that can withstand the higher temperature process steps as the insulator between the bit lines. Then, the higher dielectric constant material is removed using an etch that is selective to the bit line metal, and the low-k dielectric material is deposited. The low-k material may then be planarized to the top of the bit lines, and further low-k material deposited as an inter-level dielectric. Alternatively, sufficient low-k material is deposited in a single step to both fill the gaps between the bit lines as well as serve as an inter-level dielectric, and then the low-k dielectric material is planarized. Standard processing may then be carried out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.