Method and system for integrated circuit backside navigation
US7135123B1 · kind B1 · utility
16Cited by
4References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2004 |
| Grant date | Nov 14, 2006 |
| Priority date | — |
| Expiry date | Aug 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The backside navigation method of the present invention includes milling a fiducial opening through the substrate of an integrated circuit. The milling process is stopped when the fiducial opening reaches the bottom of a trench isolation structure. The trench isolation structure delineated by the fiducial opening may be imaged and registered to a computer aided design layout image to achieve sub-micron navigation resolution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.