Method of fabricating an integrated circuit channel region
US7138302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2004 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Feb 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/791
Abstract
An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.