Advanced technique for forming a transistor having raised drain and source regions

US7138320B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Ralf van Bentum · Radebeul, DE
• Scott Luning · San Francisco, US
• Andy Wei · Queensbury, US

Key dates

• Filing date: Oct 24, 2004
• Grant date: Nov 21, 2006
• Expiry date: Dec 19, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/018

Abstract

By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.