High-density MOS transistor
US7141837B2 · kind B2 · utility
6Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jul 31, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6735
Abstract
A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.