DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same

US7141845B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Dirk Manger · Dresden, DE
• Till Schloesser · Dresden, DE
• Rolf Weis · Dresden, DE
• Bernd Goebel · Dresden, DE
• Wolfgang Mueller · Garden City, US

Key dates

• Filing date: Jul 23, 2004
• Grant date: Nov 28, 2006
• Expiry date: Jul 23, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/485

Abstract

Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.