Double-gated silicon-on-insulator (SOI) transistors with corner rounding
US7141854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2005 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jul 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6213
Abstract
A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.