Magnetoresistive memory SOI cell
US7148531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2005 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | May 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A ferromagnetic thin-film based digital memory having a substrate formed of a base supporting an electrically insulating material primary substrate layer in turn supporting a plurality of current control devices each having an interconnection arrangement with each of said plurality of current control devices being separated from one another by spacer material therebetween and being electrically interconnected with information storage and retrieval circuitry. A plurality of bit structures are each supported on and electrically connected to a said interconnection arrangement of a corresponding one of said plurality of current control devices and have magnetic material films in which a characteristic magnetic property is substantially maintained below an associated critical temperature above which such magnetic property is not maintained of which two are separated by at least one intermediate layer of a nonmagnetic material having two major surfaces on opposite sides thereof. A plurality of word line structures located across from a corresponding one of the bit structures on an opposite side of the intermediate layer of a corresponding one of said bit structures from its interconnecti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.