High-performance electrostatic clamp comprising a resistive layer, micro-grooves, and dielectric layer
US7151658B2 · kind B2 · utility
5Cited by
16References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2003 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Jul 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02N13/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electrostatic clamp for securing a semiconductor wafer during processing. The electrostatic clamp includes a base member, a first dielectric layer, a second dielectric layer having a gas pressure distribution micro-groove network formed therein, a gas gap positioned between a backside of a semiconductor wafer and the second dielectric layer, and a pair of high voltage electrodes positioned between the first dielectric layer and the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.