Interconnection structure of semiconductor device
US7154184B2 · kind B2 · utility
7Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2003 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Jan 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.