Polishing apparatus and method for forming an integrated circuit
US7156726B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2001 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Apr 22, 2022 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB24D7/14
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
In one embodiment, a dielectric layer (144, 156) overlying a semiconductor substrate (28) is uniformly polished. During polishing, the perimeter (32) of the semiconductor substrate (28) overlies a peripheral region (16, 48, 66, 86, 120) of a polishing pad (6, 42, 60, 80, 100) and an edge portion (36) of the front surface of semiconductor substrate (28) is not in contact with the front surface (18, 50, 68, 88, 122) of the polishing pad (6, 42, 60, 80, 100), in the peripheral region (16, 48, 66, 86, 120). As a result, the polishing rate at the edge portion (36) of the semiconductor substrate (28) is reduced, and the semiconductor substrate (28) is polished with improved center to edge uniformity. Since the semiconductor substrate (28) is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion (36) of the semiconductor substrate (28) are not over polished.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.