Semiconductor memory device having a plurality of memory areas with memory elements
US7158405B2 · kind B2 · utility
1Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2002 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Sep 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the memory areas. During operation, each selection device can be assigned in a controllable manner to a plurality of memory areas such that selectively each of the selection devices can carry out an addressing and selection in one of the assigned memory areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.