VLSI fabrication processes for introducing pores into dielectric materials
US7166531B1 · kind B1 · utility
119Cited by
59References
36Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 31, 2005 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Jan 31, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/96
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.