Method and apparatus for performance enhancement in an asymmetrical semiconductor device
US7166897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2004 |
| Grant date | Jan 23, 2007 |
| Priority date | — |
| Expiry date | Dec 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
Abstract
A method and apparatus is presented that provides performance enhancement in a semiconductor device. In one embodiment, a first current region (64, 76, 23), a channel region and a second current region (75, 33, 66) are adjacent each other. The second current region (75, 33, 66) has a content of a first element of an alloy greater than a content of the first element in the first current region (64, 76, 23), wherein the second current region (75, 33, 66) has a content of the first element greater than a content of the first element in the channel region, the alloy further comprises a second element, the first element has a first valence number, and the second element has a second valence number. Furthermore, the sum of the first valence number and the second valence number is eight.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.