Material architecture for the fabrication of low temperature transistor
US7169675B2 · kind B2 · utility
149Cited by
6References
49Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 7, 2004 |
| Grant date | Jan 30, 2007 |
| Priority date | — |
| Expiry date | Jul 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.