Lead-free integrated circuit package structure
US7180170B2 · kind B2 · utility
1Cited by
18References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2005 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jan 24, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.