Overlay marks, methods of overlay mark design and methods of overlay measurements
US7181057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2002 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jun 28, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An overlay mark for determining the relative position between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of a substrate is disclosed. The overlay mark includes a plurality of working zones, which are used to calculate alignment between a first and a second layer of the substrate or between a first and a second pattern on a single layer of the substrate. Each of the working zones is positioned within the perimeter of the mark. Each of the working zones represents a different area of the mark. The working zones are configured to substantially fill the perimeter of the mark such that the combined area of the working zones is substantially equal to the total area of the mark.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.