Memory array including isolation between memory cell and dummy cell portions
US7183608B2 · kind B2 · utility
3Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Sep 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A semiconductor memory device structure includes an isolation region formed along an edge of a memory cell portion adjacent to a dummy cell portion to isolate the memory cell portion from leakage current generated in the dummy cell portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.