High speed switching MOSFETS using multi-parallel die packages with/without special leadframes
US7183616B2 · kind B2 · utility
20Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Sep 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This invention discloses a method for configuring a power MOSFET package by packaging several paralleled and separated MOSFET chips in the assembly. The method further includes a step of connecting the gate pad on each of these MOSFET chips with a low-resistance gate bus. The package resistance and inductance are significantly reduced and switching speed and heat dissipation are substantially improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.