Highly efficient segmented word line MRAM array
US7184302B2 · kind B2 · utility
25Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Mar 30, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Jun 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an MRAM array based on MTJs, the size of segmented word line select transistors and their associated connections become a significant overhead, especially when the operating point is chosen deep along the hard axis of the asteroid curve. This problem has been overcome by placing the big segmented word line select transistors under the MTJ array and reducing the overall MRAM cell array down to a level comparable to a simple Cross Point MRAM array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.