Method for programming multi-bit charge-trapping memory cell arrays
US7184317B2 · kind B2 · utility
5Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Sep 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired programming of a neighboring memory cell is avoided by the application of an intermediate inhibit voltage to an adjacent bitline. This is done by precharging all the bitlines to the inhibit voltage, either by successively applying the inhibit voltage to every bitline individually or by applying both the upper and the lower programming voltage to one half of the bitlines and then short-circuiting all the bitlines to produce an intermediate voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.