Reducing memory failures in integrated circuits
US7187602B2 · kind B2 · utility
10Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2003 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Jun 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.