Structure and method of applying stresses to PFET and NFET transistor channels for improved performance
US7193254B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 30, 2004 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Nov 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
A semiconductor device structure is provided which includes a first semiconductor device; a second semiconductor device; and a unitary stressed film disposed over both the first and second semiconductor devices. The stressed film has a first portion overlying the first semiconductor device, the first portion imparting a first magnitude compressive stress to a conduction channel of the first semiconductor device, the stressed film further having a second portion overlying the second semiconductor device, the second portion not imparting the first magnitude compressive stress to a conduction channel of the second semiconductor device, the second portion including an ion concentration not present in the second portion such that the second portion imparts one of a compressive stress having a magnitude much lower than the first magnitude, zero stress, and a tensile stress to the conduction channel of the second semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.