Method of manufacturing an intralevel decoupling capacitor
US7195971B2 · kind B2 · utility
16Cited by
38References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2005 |
| Grant date | Mar 27, 2007 |
| Priority date | — |
| Expiry date | Feb 28, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/435
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.