Patent · US Expired

Test circuit and method for testing an integrated memory circuit

US7197678B2 · kind B2 · utility

3Cited by

7References

12Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Carsten Ohlhoff · Hersbruck, DE
Peter Beer · Waldshut-Tiengen, DE

Key dates

Filing date	Jul 3, 2003
Grant date	Mar 27, 2007
Priority date	—
Expiry date	Nov 14, 2024

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/401
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A test circuit for testing a memory circuit has a data input line for providing test data and a comparator unit. The comparator unit is connected to the data input line and to the memory circuit for comparing the test data written into the memory circuit with the test data read from the memory area. The data input line is connected to the memory circuit via a data change circuit. The data change circuit is controllable depending on a result of a comparison in the comparator unit such that when an error occurs, subsequent test data can be written in an altered manner to the memory circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.