Method for manufacturing a stack arrangement of a memory module

US7198979B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Jochen Thomas · Munich, DE
• Wolfgang Hetzel · Nattheim, DE
• Ingo Wennemuth · Munich, DE

Key dates

• Filing date: Nov 4, 2003
• Grant date: Apr 3, 2007
• Expiry date: Apr 13, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/19107
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of stacking semiconductor chips includes providing four semiconductor chips that each include a top surface with central bond pads. Each of the bond pads is electrically coupled to second bond pads located in a peripheral portion of the semiconductor chip through a conductive layer. The first and the second semiconductor chips are arranged alongside one another on a carrier substrate. The second bond pads from the first and second semiconductor chips are bonded to corresponding landing pads on the substrate. The third semiconductor chip is then stacked over the first semiconductor chip and the fourth semiconductor chip over the second semiconductor chip. The second bond pads of the third and fourth semiconductor chips can then be bonded to contact pads of the substrate. The substrate can then be separated into a first stack that includes the first and third semiconductor chips and a second stack that includes the second and fourth semiconductor chips.