Stress-reduced layer system for use in storage capacitors

US7199414B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Matthias Goldbach · Dresden, DE
• Bernhard Sell · Dresden, DE
• Annette Sanger · Dresden, DE

Key dates

• Filing date: Feb 17, 2004
• Grant date: Apr 3, 2007
• Expiry date: Jun 6, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/038

Abstract

The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.