CMOS transistor structure including film having reduced stress by exposure to atomic oxygen
US7202516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2005 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Dec 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.