Integrated dynamic random access memory element, array and process for fabricating such elements
US7202518B2 · kind B2 · utility
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5References
32Claims
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Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Apr 10, 2007 |
| Priority date | — |
| Expiry date | Jul 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend between the source and drain regions. A channel is provided in the intermediate portion of the transistor for each cell. A polarization electrode is placed between the respective intermediate portions of the two transistors. This polarization electrode is capacitively coupled to the intermediate portion of each transistor and is used to store the first and second bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.