Patent · US Expired

Integrated circuit

US7203883B2 · kind B2 · utility

0Cited by

6References

32Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Aurel von Campenhausen · Munich, DE
Marcin Gnat · Birkenfeld, DE
Joerg Vollrath · Richmond, US
Ralf Schneider · Birkenfeld, DE

Key dates

Filing date	Mar 23, 2005
Grant date	Apr 10, 2007
Priority date	—
Expiry date	Oct 5, 2025

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated semiconductor memory, which can be operated in a normal operating state and a test operating state, includes a current pulse circuit with an input terminal for applying an input signal. The current pulse circuit is connected to an output terminal via an interconnect for carrying a current. In the test operating state, the current pulse circuit generates at least one first current pulse with a first, predetermined time duration in a first test cycle and at least one second current pulse with a second, unknown time duration in a subsequent second test cycle. In addition to a first current flowing on the interconnect in the normal operating state, a second current flows on the interconnect during the first test cycle and a third current flows during the second test cycle in the test operating state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.