Method of fabricating mobility enhanced CMOS devices
US7205206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2004 |
| Grant date | Apr 17, 2007 |
| Priority date | — |
| Expiry date | Mar 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
Abstract
Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.