Deposition of diffusion barrier
US7214605B2 · kind B2 · utility
2Cited by
11References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2003 |
| Grant date | May 8, 2007 |
| Priority date | — |
| Expiry date | Dec 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a stacked wafer structure with decreased failures. In one embodiment, there is a barrier layer deposited on exposed surfaces of conductors that extend across a distance between first and second device structures. The barrier layer may prevent diffusion and electromigration of the conductor material, which may decrease incidences of shorts and voids in the stacked wafer structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.