Recessed gate for an image sensor
US7217968B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2004 |
| Grant date | May 15, 2007 |
| Priority date | — |
| Expiry date | Dec 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/80
Abstract
A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.