Patent · US Expired

Integrated semiconductor circuit and method for testing the same

US7224627B2 · kind B2 · utility

2Cited by

6References

9Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Marcin Gnat · Birkenfeld, DE
Aurel von Campenhausen · Munich, DE
Joerg Vollrath · Richmond, US
Ralf Schneider · Birkenfeld, DE

Key dates

Filing date	Apr 7, 2005
Grant date	May 29, 2007
Priority date	—
Expiry date	Sep 28, 2025

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.