Methods for fabricating a germanium on insulator wafer

US7229898B2 · kind B2 · utility

Assignee

• S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES · FR

Inventors

• Konstantin Bourdelle · Castelsarrasin, FR
• Fabrice Letertre · Grenoble, FR
• Bruce Faure · Grenoble, FR
• Christophe Morales · Le Pont-de-Claix, FR
• Chrystel Deguet · Meylan, FR

Key dates

• Filing date: Jan 4, 2005
• Grant date: Jun 12, 2007
• Expiry date: Jun 16, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76254
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Improved fabrication processes for manufacturing GeOI type wafers are disclosed. In an implementation, a method for fabricating a germanium on insulator wafer includes providing a source substrate having a surface, at least a layer of germanium and a weakened area. The weakened area is located at a predetermined depth in the germanium layer of the source substrate and is generally parallel to the source substrate surface. The technique also includes providing a germanium oxynitride layer in or on the source substrate, bonding the source substrate surface to a handle substrate to form a source-handle structure, and detaching the source substrate from the source-handle structure at the weakened area of the source substrate to create the germanium on insulator wafer having, as a surface, a useful layer of germanium.