Recessed semiconductor device
US7229903B2 · kind B2 · utility
13Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2004 |
| Grant date | Jun 12, 2007 |
| Priority date | — |
| Expiry date | Sep 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.