Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same
US7232743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Nov 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor structure having a high-strained crystalline layer with a low crystal defect density is disclosed. The structure includes a substrate having a first material comprising germanium or a Group(III)-Group(V)-semiconductor or alloy thereof. In addition, a crystalline epitaxial first layer, comprising a graded buffer layer and a substantially relaxed layer, is provided. The buffer layer is sufficiently relaxed to provide relaxation of the substantially relaxed layer deposited thereon. A further layer may be provided on the first layer, and the transfer of at least the further layer is facilitated by providing a weakened zone in the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.