Cecile Aulnette
29Patents
8h-index
24Co-inventors
71Inventor score
Filing activity: Jul 8, 2003 → Feb 1, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6955971B2 | Semiconductor structure and methods for fabricating same | Emerging Cross-Sectional Technologies | 69 | Expired |
| US6991995B2 | Method of producing a semiconductor structure having at least one support substrate and an ultrathin layer | Electricity | 29 | Expired |
| US7407867B2 | Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate | Emerging Cross-Sectional Technologies | 17 | Active |
| US7459374B2 | Method of manufacturing a semiconductor heterostructure | Electricity | 17 | Active |
| US7018910B2 | Transfer of a thin layer from a wafer comprising a buffer layer | Emerging Cross-Sectional Technologies | 16 | Expired |
| US6991956B2 | Methods for transferring a thin layer from a wafer having a buffer layer | Electricity | 12 | Expired |
| US7256075B2 | Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer | Electricity | 12 | Expired |
| US7008857B2 | Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom | Electricity | 9 | Expired |
| US7232488B2 | Method of fabrication of a substrate for an epitaxial growth | Emerging Cross-Sectional Technologies | 6 | Expired |
| US8367521B2 | Manufacture of thin silicon-on-insulator (SOI) structures | Electricity | 6 | Active |
| US7115481B2 | Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6908774B2 | Method and apparatus for adjusting the thickness of a thin layer of semiconductor material | Emerging Cross-Sectional Technologies | 6 | Expired |
| US7232743B2 | Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same | Electricity | 6 | Expired |
| US7446019B2 | Method of reducing roughness of a thick insulating layer | Electricity | 6 | Active |
| US7033905B2 | Recycling of a wafer comprising a buffer layer after having separated a thin layer therefrom by mechanical means | Electricity | 5 | Expired |
| US7078353B2 | Indirect bonding with disappearance of bonding layer | Emerging Cross-Sectional Technologies | 5 | Expired |
| US6995427B2 | Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same | Electricity | 4 | Expired |
| US7544976B2 | Semiconductor heterostructure | Electricity | 4 | Active |
| US9954139B2 | Multiple transfer assembly process | Emerging Cross-Sectional Technologies | 3 | Active |
| US7375008B2 | Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof | Electricity | 3 | Expired |
| US7572714B2 | Film taking-off method | Electricity | 2 | Active |
| US8324075B2 | Methods for recycling substrates and fabricating laminated wafers | Emerging Cross-Sectional Technologies | 2 | Active |
| US7602046B2 | Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof | Electricity | 2 | Expired |
| US9018678B2 | Method for forming a Ge on III/V-on-insulator structure | Electricity | 0 | Active |
| US7378729B2 | Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.