Polycrystalline silicon layer with nano-grain structure and method of manufacture
US7232774B2 · kind B2 · utility
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Key dates
| Filing date | Jan 20, 2004 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Jun 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/662
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50° C. above the 550° C. crystallization temperature of silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.