Method for forming a semiconductor device having a silicide layer
US7235471B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Jun 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device includes providing a semiconductor substrate, forming an insulating layer over the semiconductor substrate, forming a conductive layer over the insulating layer, forming a first metal silicide layer over the conductive layer, patterning the conductive layer to form a patterned first layer, wherein the patterned first layer is a part of a control electrode, patterning the first metal silicide layer to form a patterned first metal silicide layer over the control electrode so that the patterned first metal silicide layer remains over the control electrode, and forming a second metal silicide over the patterned metal silicide layer, wherein the second metal silicide layer has a thickness greater than the thickness of first metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.