Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions

US7238578B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Gert Burbach · Dresden, DE
• Rolf Stephan · Dresden, DE
• Karsten Wieczorek · Dresden, DE
• Manfred Horstmann · Dresden, DE

Key dates

• Filing date: Apr 26, 2005
• Grant date: Jul 3, 2007
• Expiry date: Feb 3, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.