Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration
US7238580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2005 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Dec 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.