Integration of ALD/CVD barriers with porous low k materials
US7244683B2 · kind B2 · utility
35Cited by
83References
22Claims
0Family size
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Key dates
| Filing date | Dec 19, 2003 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Jun 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for processing substrates is provided. The method includes depositing and etching a low k dielectric layer on a substrate, pre-cleaning the substrate with a plasma, and depositing a barrier layer on the substrate. Pre-cleaning the substrate minimizes the diffusion of the barrier layer into the low k dielectric layer and/or enhances the deposition of the barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.