Techniques for reducing leakage current in memory devices
US7245548B2 · kind B2 · utility
12Cited by
5References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2004 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Jul 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.