Integrated circuit having structural support for a flip-chip interconnect pad and method therefor

US7247552B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Scott K. Pozder · Austin, US
• Kevin J. Hess · Austin, US
• Pak K. Leung · Kowloon, CN
• Edward O. Travis · Austin, US
• Brett P. Wilkerson · Austin, US
• David G. Wontor · Allen, US
• Jie Zhao · Seoul, KR

Key dates

• Filing date: Jan 11, 2005
• Grant date: Jul 24, 2007
• Expiry date: Nov 26, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/14
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.